`include "PRV564Config.v"
`include "PRV564Define.v"
module AQRQ_Difftest
(
    input  wire                 ICache_AQ_V,      DCache_AQ_V,
    input  wire [7:0]           ICache_AQ_ID,     DCache_AQ_ID,
    input  wire [7:0]           ICache_AQ_CMD,    DCache_AQ_CMD,
    input  wire                 ICache_AQ_CI,     DCache_AQ_CI,
    input  wire                 ICache_AQ_WT,     DCache_AQ_WT,
    input  wire [15:0]          ICache_AQ_BSEL,   DCache_AQ_BSEL,
    input  wire [127:0]                           DCache_AQ_WDATA,
    input  wire [`XLEN-1:0]     ICache_AQ_ADDR,   DCache_AQ_ADDR,
    output wire                  ICache_AQ_FULL,   DCache_AQ_FULL,
    output reg                   ICache_RQ_V,      DCache_RQ_V,
    output reg  [7:0]            ICache_RQ_ID,     DCache_RQ_ID,
    output wire                  ICache_RQ_WRERR,  DCache_RQ_WRERR,
    output wire                  ICache_RQ_RDERR,  DCache_RQ_RDERR,
    output wire                  ICache_RQ_RDY,    DCache_RQ_RDY,
    output reg  [127:0]          ICache_RQ_RDATA,  DCache_RQ_RDATA,
    input  wire                 ICache_RQ_ACK,    DCache_RQ_ACK,
    input GLBi_CLK
);
wire [63:0] InstrBuf;
wire wrvalid;
wire [127:0]wdata;
wire [15:0]wmask;
wire [63:0]wmaskl,wmaskh;
wire [63:0]waddr;
assign waddr=(DCache_AQ_ADDR-32'h8000_0000)>>3;
assign wdata=DCache_AQ_WDATA;
assign wmask=DCache_AQ_BSEL;
assign wmaskl=  {
                    {8{wmask[7]}},
                    {8{wmask[6]}},
                    {8{wmask[5]}},
                    {8{wmask[4]}},
                    {8{wmask[3]}},
                    {8{wmask[2]}},
                    {8{wmask[1]}},
                    {8{wmask[0]}}
                };
assign wmaskh=  {
                    {8{wmask[15]}},
                    {8{wmask[14]}},
                    {8{wmask[13]}},
                    {8{wmask[12]}},
                    {8{wmask[11]}},
                    {8{wmask[10]}},
                    {8{wmask[9]}},
                    {8{wmask[8]}}
                };
always@(posedge GLBi_CLK)
begin
    if(ICache_RQ_V & !ICache_RQ_ACK)begin        //洪啸宇过来挨打
        ICache_RQ_V     <=ICache_RQ_V;
        ICache_RQ_RDATA <=ICache_RQ_RDATA;      
        ICache_RQ_ID    <=ICache_RQ_ID;
    end
    else begin                                  //current no istruction stall, keep on going
        ICache_RQ_V             <=ICache_AQ_V;
        ICache_RQ_ID            <=ICache_AQ_ID;
        ICache_RQ_RDATA[63:0]   <=ram_read_helper(1'b1, (ICache_AQ_ADDR>>3)&64'hFFFF_FFFF_FFFF_FFFE);
        ICache_RQ_RDATA[127:64] <=ram_read_helper(1'b1, (ICache_AQ_ADDR>>3)|64'h01);
    end
    

    if(DCache_RQ_V & !DCache_RQ_ACK)begin        
        DCache_RQ_V     <=DCache_RQ_V;
        DCache_RQ_RDATA <=DCache_RQ_RDATA;      
        DCache_RQ_ID    <=DCache_RQ_ID;
    end
    else begin                                  //current no istruction stall, keep on going
        DCache_RQ_V             <=DCache_AQ_V;
        DCache_RQ_ID            <=DCache_AQ_ID;
        DCache_RQ_RDATA[63:0]   <=ram_read_helper(1'b1, waddr&64'hFFFF_FFFF_FFFF_FFFE);//(DCache_AQ_ADDR>>3)
        DCache_RQ_RDATA[127:64] <=ram_read_helper(1'b1, waddr|64'h01);//(DCache_AQ_ADDR>>3)
        //if(DCache_AQ_CMD==`LSU_WRITE)
        //begin
            ram_write_helper(waddr&64'hFFFF_FFFF_FFFF_FFFe,wdata[63:0],wmaskl,DCache_AQ_CMD==`LSU_WRITE);
            ram_write_helper(waddr|64'h01,wdata[127:64],wmaskh,DCache_AQ_CMD==`LSU_WRITE);
        //end
    end
    
end
assign ICache_AQ_FULL=ICache_RQ_V & !ICache_RQ_ACK;
assign DCache_AQ_FULL=DCache_RQ_V & !DCache_RQ_ACK;
assign ICache_RQ_WRERR=0;
assign DCache_RQ_WRERR=0;
assign ICache_RQ_RDERR=0;
assign DCache_RQ_RDERR=0;
assign ICache_RQ_RDY=1'b1;
assign DCache_RQ_RDY=1'b1;
endmodule
